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general description the max31790 controls the speeds of up to six fans using six independent pwm outputs. the desired fan speeds (or pwm duty cycles) are written through the i 2 c interface. the outputs drive 4-wire fans directly, or can be used to modulate the fans power terminals using an external pass transistor. tachometer inputs monitor fan tachometer logic outputs for precise ( q 1%) monitoring and control of fan rpm as well as detection of fan failure. six pins are dedicated tachometer inputs. any of the six pwm outputs can also be configured to serve as tachometer inputs. the pwm_start inputs select the pwm output status at startup to ensure appropriate fan drive when power is first applied. to ensure low acoustic impact of fan control, all changes in pwm duty cycle take place at a controlled, program - mable rate. the max31790s 3.0v to 5.5v supply voltage range and i 2 c-compatible interface make it ideal for fan control in a wide range of cooling applications. the max31790 is available in a 28-pin tqfn package and operates over the -40 n c to +125 n c temperature range. features s controls up to six independent fans with pwm drive s up to 12 tachometer inputs s controlled duty cycle rate-of-change for best acoustics s i 2 c bus interface with timeout and watchdog s 3.0v to 5.5v supply voltage range s 1.5ma (typ) operating supply current applications servers networking telecom 19-6540; rev 0; 12/12 ordering information appears at end of data sheet. typical operating circuit max31790 fan1 v 4-wire fan v cc v cc r pu v cc 3.0v to 5.5v crystal (optional) 0.1f 12pf 12pf pwmout2 tach2 pwmout3 tach3 pwm output driver, tach monitor i 2 c interface, registers, and control logi c pwmout4 tach4 pwmout5 tach5 pwmout1 sda v cc xtal2 xtal1 tach1 scl fan_fail host interface set power-up values clkout full_speed pwmout6 tach6 gnd 6 channels pwm_start1 pwm_start0 freq_start spin_start wd_start add1 add0 for related parts and recommended products to use with this part, refer to: www.maximintegrated.com/max31790.related max31790 6-channel pwm-output fan rpm controller evaluation kit available for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com.
2 voltage range on v cc , sda, scl, add0, add1, fan_fail , pwmoutn relative to gnd ........... -0.3v to +6.0v voltage range on tachn, wd_start, spin_start, freq_start, clkout, full_speed , pwm_startn relative to gnd .............. -0.3v to v cc + 0.3v (not to exceed +6.0v) input current at any pin .................................................... +5ma package input current .................................................... +20ma continuous power dissipation (t a = +70 n c) tdfn (derate 20.8 mw/ n c above +70 n c) ............. 1666.7 mw operating temperature range ........................ -40 n c to +125 n c storage temperature range ............................ -65 n c to +150 n c junction temperature ..................................................... +150 n c esd protection (all pins, hbm) (note 1) ........................ q 2000v lead temperature (soldering, 10s) ................................ +300 n c soldering temperature (reflow) ...................................... +260 n c absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operating conditions (t a = -40c to +125c, unless otherwise noted.) (notes 2, 3) electrical characteristics (t a = -40c to +125c, typical values are v cc = 3.3v, t a = +25c, unless otherwise noted.) (notes 2, 3) note 1: human body model, 100pf discharged through a 1.5k resistor. parameter symbol conditions min typ max units operating supply voltage v cc 3.0 3.3 5.5 v input high voltage v ih v cc x 0.7 v input low voltage v il v cc x 0.3 v parameter symbol conditions min typ max units quiescent supply current (note 4) i cc 3.0v < v cc < 3.6v 1.5 3 ma 4.5v < v cc < 5.5v 2.5 8 por threshold v por 2 v watchdog timer accuracy f tosc = 32.768khz (note 5) -0.5 +0.5 s output low voltage (sda, fan_ fail , pwmoutn, clkout) i ol = 3ma 0.4 v output high voltage (clkout) i oh = 1ma, v cc = 3.0v 2.7 v xtal1 input threshold 0.85 v input leakage i l (note 6) -1 +1 f a input capacitance all digital inputs 5 pf max31790 6-channel pwm-output fan rpm controller maxim integrated
3 fan control characteristics (t a = -40c to +125c, typical values are v cc = 3.3v, t a = +25c, unless otherwise noted.) (note 3) i 2 c ac electrical characteristics (v cc = +3.0v to +5.5v, t a = -40c to +125c, timing referenced to v il(max) and v ih(min) , unless otherwise noted.) (notes 3, 8) ( figure 1 ) parameter symbol conditions min typ max units serial clock frequency f scl dc 400 khz bus free time between stop and start conditions t buf 1.3 f s start condition hold time t hd:sta 0.6 f s stop condition setup time t su:sto 90% of scl to 10% of sda 600 ns clock low period t low 1.3 f s clock high period t high 0.6 f s start condition setup time t su:sta 90% of scl to 90% of sda 100 ns data setup time t su:dat 10% of sda to 10% of scl 100 ns data in hold time t hd:dat 10% of scl to 10% of sda (note 9) 0 0.9 f s maximum receive scl/sda rise time t r (note 10) 300 ns minimum receive scl/sda rise time t r (note 10) 20 + 0.1 x c b ns parameter symbol conditions min typ max units pwm resolution 9 9 bits pwm frequency accuracy -6 +6 % tach count resolution 11 11 bits tach count oscillator and clkout clock f tosc (note 7) 32.768 khz tach count oscillator and clkout accuracy (note 7) f err:tosc using internal oscillator: t a = +25 c, v cc = 3.3v -0.5 +0.5 % using internal oscillator: 0 c < t a < +70 c, 3.0v < v cc < 3.6v -2.5 +2.5 using internal oscillator: -40 c < t a < +125 c, 3.0v < v cc < 3.6v -4.0 +4.0 using internal oscillator: -40 c < t a < +125 c, 3.0v < v cc < 5.5v -7.0 +7.0 using external crystal -0.1 +0.1 tach minimum input pulse width t tachmin pulse width must be greater than this value to be detected 25 75 f s max31790 6-channel pwm-output fan rpm controller maxim integrated
4 i 2 c ac electrical characteristics ( continued ) (v cc = +3.0v to +5.5v, t a = -40c to +125c, timing referenced to v il(max) and v ih(min) , unless otherwise noted.) (notes 3, 8) ( figure 1 ) note 2: all voltages referenced to ground. currents entering the ic are specified as positive. note 3: limits are 100% production tested at t a = +25c and/or t a = +85c. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. typical values are not guaranteed. note 4: sda = scl = v cc , pwm active with pwm_frequency = 25khz. note 5: the watchdog timer is derived from f tosc and the watchdog timer accuracy specifications do not include the oscillators associated error f err:tosc . note 6: applies to pins sda, scl, pwm_startn, wd_start, freq_start, spin_start, addn, tachn, pwmoutn, full_speed . note 7: f tosc is used to measure fan speed by counting the number of 8192hz (f tosc /4) clock cycles that take place during a selectable number of tachometer periods. note 8: all timing specifications are guaranteed by design. note 9: a master device must provide a hold time of at least 300ns for the sda signal to bridge the undefined region of scls fall - ing edge. note 10: c b total capacitance of one bus line in pf. note 11: holding the sda line low for a time greater than t timeout causes the device to reset sda to the idle state of the serial bus communication (sda set high). external crystal parameters (note 3) parameter symbol conditions min typ max units maximum receive scl/sda fall time t f (note 10) 300 ns minimum receive scl/sda fall time t f (note 10) 20 + 0.1 x c b ns transmit sda fall time t f 10pf p c b p 400pf (note 10) 20 + 0.1 x c b 250 ns pulse width of suppressed spike t sp 35 ns sda time low for reset of serial interface t timeout (note 11) 25 45 ms parameter symbol conditions min typ max units crystal oscillator startup time 1 s nominal frequency f o 32.768 khz series resistance esr 50 k i load capacitance c l 12 pf max31790 6-channel pwm-output fan rpm controller maxim integrated
5 typical operating characteristics (t a = +25c, unless otherwise noted.) figure 1. i 2 c timing diagram scl note: timing is referenced to v il(max) and v ih(min) . sda stop start repeated start t buf t hd:sta t hd:dat t su:dat t su:sto t hd:sta t sp t su:sta t high t r t f t low power-supply current vs. power-supply voltage max31790 toc01 supply voltage (v) supply current (ma) 5.5 4.5 3.5 1 2 3 4 0 2.5 6.5 pwm frequency = 25khz 1.47khz pwm frequency = 25hz power-supply current vs. temperature max31790 toc02 temperature(c) supply current (ma) 100 50 0 1 2 3 4 0 -50 150 pwm frequency = 25khz v dd = 3.3v pwm frequency = 25hz max31790 6-channel pwm-output fan rpm controller maxim integrated
6 pin configuration pin description pin name function 1 freq_start this input is sampled at power-up and sets the power-up value for the pwm output frequency. see the register map for values. 2 spin_start this input is sampled at power-up and sets the initial spin-up behavior. see the register map for values. 3 add1 address select inputs. sampled at the start of every i 2 c transaction. one of 16 possible addresses can be selected by connecting add0 and add1 to gnd, v cc , sda, or scl. 4 add0 5 wd_start this input is sampled at power-up and sets the initial i 2 c watchdog behavior. see the register map for values. 6 xtal2 pins for connecting to optional 32,768hz crystal. the crystal can be used when the best rpm precision is required. at por the internal oscillator is used, and a nominal 32,768hz clock is pro - duced at clkout. if a crystal is connected between xtal1 and xtal2, the crystal oscillator can be enabled by writing to a register. if no crystal is present, ground xtal1 and leave xtal2 uncon - nected. 7 xtal1 8 gnd ground 26 27 25 24 10 9 11 spin_start add0 wd_start xtal2 xtal1 12 freq_start pwmout1 pwmout2 tach2 v cc pwmout3 tach3 12 pwm_start0 45 67 20 21 19 17 16 15 pwm_start1 full_speed pwmout5 tach5 pwmout6 tach6 add1 tach1 3 18 28 8 clkout gnd ep + fan_fail 23 13 tach4 scl 22 14 pwmout4 sda tqfn (4mm x 4mm) top view max31790 max31790 6-channel pwm-output fan rpm controller maxim integrated
7 pin description (continued) pin name function 9 tach6 logic/analog inputs for tach signals. if a fan has a logic tach output, it can be used for rpm con - trol. for a 2-wire fan, analog input can be used for fan-failure detection. also functions as a locked rotor input. 11 tach5 13 tach4 15 tach3 17 tach2 19 tach1 10 pwmout6 open-drain output to 4-wire fans pwm input or (less frequently) to power transistor modulating fan power supply. can also be used as a tachometer signal input. can be pulled up as high as 5.5v. 12 pwmout5 14 pwmout4 16 pwmout3 18 pwmout2 20 pwmout1 21 v cc power-supply input. 3.3v nominal. bypass v cc to gnd with a 0.1 f f capacitor. 22 sda i 2 c serial-data input/output, open drain. can be pulled up to 5.5v regardless of v cc . 23 scl i 2 c serial-clock input. can be pulled up to 5.5v regardless of v cc . 24 fan_fail active-low, open-drain fan-failure output. active only when fault is present. 25 pwm_start0 these inputs are sampled at power-up and set the power-up value for all pwmout duty cycles. see the register map for values. 26 pwm_start1 27 full_speed when low, this input forces all pwm outputs to 100%. exception: if a fan has failed and duty cycle = 0 on failure has been selected for that fan. 28 clkout cmos push-pull 32,768hz clock output. signal generated from internal oscillator when external crystal is not used. if a crystal is connected between xtal1 and xtal2 and enabled, the crystal oscillator generates the output. output is always active. ep exposed pad. connect to gnd. max31790 6-channel pwm-output fan rpm controller maxim integrated
8 block diagram max31790 pwmout6 tachn enabl e gnd v cc xtal2 xtal1 pwmout5 pwmout4 pwmout3 pwmout2 pwmout1 tach6 tach5 tach4 tach3 tach2 tach1 full_speed tach12 tach11 tach10 tach9 tach8 tach7 pulse-width modulator fan controller logic fan tachometer inputs fan fail logic power control divider user memory por pin sample logic watchdog timer slave address decode logic i 2 c interface block i 2 c bus timeout internal oscillator osc bit clkout oscillator circuit fan_fail sda scl add0 add1 wd_start spin_start freq_start pwm_start1 pwm_start0 max31790 6-channel pwm-output fan rpm controller maxim integrated
9 detailed description the max31790 controls the speeds of up to six fans using six independent pwm outputs. the desired fan speeds (or pwm duty cycles) are written through the i 2 c interface. the outputs drive 4-wire fans directly or can be used to control 2-wire or 3-wire fans by modulating the fans power supply voltage. modulating the power supply voltage can be achieved by various techniques and are described in the controlling 2-wire and 3-wire fans section. the max31790 has two main methods for controlling fan speeds: pwm mode and rpm mode. additional level of control is achieved by the incorporated rate-of-change control that allows the device to control the max rate at which the pwm duty cycle is incremented/decremented. tachometer inputs monitor fan tachometer logic outputs for precise (1%) monitoring and control of fan rpm as well as detection of fan failure. six pins are dedicated tachometer inputs. any of the six pwm outputs can also be configured to serve as tachometer inputs, allowing for up to 12 fans to be monitored. the device can monitor the tachn inputs and determine when a fan has failed. failure is detected in various ways depending on the fan control mode. once a selectable number of fault detections has occurred, the fan_fail output asserts (if fault detection is not masked for the fan). power-on values for pwm duty cycles, pwm frequencies, fan spin-up, and the watchdog are achieved by five pin inputs. fan control the device has two main methods for controlling fan speeds: pwm mode and rpm mode. pwm mode in pwm mode, the device produces a pwm waveform that drives the fans pwm speed control input. the fans speed is proportional to the pwm duty cycle delivered to its pwm input terminal. the duty cycle is set by the fans associated pwmout target duty cycle registers and the actual duty cycle can be read from the correspond - ing pwmout duty cycle register. because the duty cycle ramps to new values at a controlled rate, the values in the two registers can be different. see the register descriptions section for details. rpm mode in rpm mode, the device monitors tachometer output pulses from the fan and adjusts the pwm duty cycle to force the fans speed to the desired value. fan speed is measured by counting the number of internal 8192hz (f tosc /4) clock cycles that take place during a select - able number of tachometer periods. the number of clock cycles counted (11-bit value) is stored in the associated tach count registers and the desired number of cycles is stored in the tach target count registers. see the register descriptions section for details. rate-of-change control sudden changes in fan speed can be easily heard by users. the device helps reduce the audibility of fan- speed changes by controlling the rate at which the pwm duty cycle is incremented. three bits in the associated fan dynamics register sets the rate at which the duty cycle is incremented/decremented. this allows the time required for an lsb of change in the pwm duty cycle to vary from 0ms to 125ms. the selected rate of change also applies when the full_speed input is asserted or when the fans are forced to 100% due to a fan failure. see the register descriptions section for details. in rpm mode when the fans speed is near the target speed, that is, when the tach count is near the tach target count, the control loop dynamics can often be improved by slowing the rate of change of the pwm duty cycle. this operates as follows: first, set a value for the count window and store it in the appropriate window register. in rpm mode, calculate the difference between the current tach count and the target tach count. if the absolute value of this difference is less than the value in the appropriate window register, the update rate of the pwm duty cycle is slowed to 1 lsb per second. when the current tach count falls outside of the window, the duty cycle rate of change reverts to the selected value. spin-up when a fan is not spinning, and a low duty cycle waveform is applied to its pwm terminal, it can fail to overcome inertia and start spinning. to overcome this potential problem, a 100% duty cycle waveform can be applied to the fans pwm input for a short time before a lower duty cycle waveform is applied. this spin-up period allows the fan to overcome inertia and begin oper - ating. spin-up is controlled using the corresponding fan max31790 6-channel pwm-output fan rpm controller maxim integrated
10 configuration register. spin-up can be disabled, or it can cause the fan to be driven with a 100% duty cycle until it produces two tachometer pulses, up to a maximum of 0.5s, 1s, or 2s. when spin-up is enabled and the duty cycle is making a transition from 0% to a value that is less than 100% (from 0% to 50%, for example), the duty cycle first goes to 100%. when two tachometer pulses have been detected, or when the maximum spin-up period has elapsed, the duty cycle drops to the target value (50% in this example). the spin_start pin sets the spin-up value at power-up. sequential fan activation when multiple high-current fans are activated simultane - ously, the startup current can stress the systems power supply. to minimize this effect, the device includes a selectable sequential fan activation feature. when select - ed, this feature inserts a short minimum delay between the activation times of fans. the bits for controlling sequential fan activation are located in the failed fan options/sequential start regis - ter. they select the time delay between fan activations to be one of the following: 0, 250ms, 500ms, 1s, 2s, or 4s. the default time is 500ms per channel. sequential fan activation applies to por, fan failure forcing the fans to full speed, and assertion of the full_speed input, which forces all the fans to full speed. in all these cases, all fans are forced to full speed. the sequence operates as follows: ? pwm1 activates. the pwm duty cycle begins to increase at the selected rate of change. ? after the selected delay time has elapsed, pwm2 acti - vates. again, the pwm duty cycle begins to increase at the selected rate of change. ? the other pwm channels activate in sequence, each delayed by the selected delay time relative to the previous channel. note that the time delay applies to unused or disabled channels. full_speed input driving this input low forces all fans to full speed with the exception of any failed fans (if 0% on failure has been selected). this input allows an external temperature switch to provide fail-safe overtemperature protection. in systems with multiple max31790s, all fan_fail outputs can be connected to all full_speed inputs, thereby providing full-speed operation if any fan fails, regardless of which max31790 controls it. this input is active even in standby mode. por options five inputs allow setup of the devices behavior at power- up. the following inputs are sampled when power is first applied to the device: wd_start: at power-up the watchdog operation is controlled by the wd_start pin. connect wd_start to v cc to enable, or to gnd to disable the watchdog func - tion. when enabled using wd_start, the timeout period is 30s. after power is applied, the watchdog function can be enabled or disabled, and the timeout period can be changed by editing the global configuration register. spin_start: at power-up, spin-up operation is controlled by the spin_start pin. connect spin_start to gnd to disable, v cc to enable spin-up for a maximum of 1s, or unconnected to enable spin-up for a maximum of 0.5s. after power is applied, the spin-up function can be enabled or disabled, and the spin-up period can be changed by editing the associated fan configuration register. pwm_start 0, pwm_start1: at power-up, the pwm output duty cycles are controlled by the pwm_start0 and pwm_start1 pins. connect pwm_start0/ pwm_start1 to gnd, v cc, or leave unconnected to achieve different duty cycles for all pwm outputs. see the pwmout target duty cycle register for the corresponding values and connections. after power is applied, the pwm duty cycles can be changed, by edit - ing that pwms associated pwmout target duty cycle register. freq_start: at power-up, all pwm output frequen - cies are controlled by the freq_start pin. connect freq_start to gnd for 30hz, v cc for 25khz, or uncon - nected for 1.47khz. after power is applied, the pwm output frequencies can be changed by editing the pwm frequency register. watchdog the device includes an optional i 2 c watchdog function that monitors the i 2 c bus for transactions. when the watchdog function is enabled, all fans (with the excep - tion of failed fans 0% on fail selected) are forced to full speed if no i 2 c transactions occur within a selected period (5s, 10s, or 30s). watchdog timing is selected using the global configuration register. max31790 6-channel pwm-output fan rpm controller maxim integrated
11 fan monitoring monitoring tachometer signals the tach inputs accept either tachometer or locked rotor output signals from 3-wire or 4-wire fans. when measuring fan speed, the device counts the number of internal 8192hz (f tosc /4)clock cycles that occur during 1, 2, 4, 8, 16, or 32 tachometer periods. (the speed of each fan is measured once per second.) the number of tachometer periods is selectable for each fan by using the appropriate fan dynamics register. tachometer pulses less than t tachmin in duration are ignored to minimize the effect of noise on the tachometer lines. the tach count for a given rpm can be obtained from the following equation: 60 tach count sr 8192 np rpm = where: np = number of tachometer pulses per revolution. most general-purpose brushless dc fans produce two tachometer pulses per revolution. sr = 1, 2, 4, 8, 16, or 32. this is the number of tachom - eter periods over which the tachometer clock is counted. see the speed range bit information described in the corresponding fan dynamics register description. the tachometer count consists of 11 bits in the tach count registers and is available in rpm and pwm modes. in rpm mode, the desired fan count is written to the associated tach target count register. in pwm mode, the desired fan duty cycle is written to the associ - ated pwmout target duty cycle register. note that the device is intended to be used with 4-wire fans. modulating a fans power supply with a pwm waveform, as is sometimes done with 2-wire and 3-wire fans, results in incorrect tachometer counts due to the periodic removal of power from the fans internal circuitry. therefore, it is suggested to use pwm mode when inter - facing with 2-wire or 3-wire fans. using pwm outputs as tachometer inputs each fan configuration register includes a pwm /tach bit that allows the pwmout to be configured as a tach input. in tach mode, the settings for tach input enable, locked rotor operation, and tach pulses counted that have been selected for a given fan channel apply to that channels tach input and also to tach signals sensed by that channels pwm output. figure 2 to figure 6 show some examples of tach-pwm connections for various fan configurations figure 2. 12 fans, 12 tach monitors, no pwm tach1 pwmout1 (tach7) tach2 pwmout2 (tach8) tach3 pwmout3 (tach9) tach4 pwmout4 (tach10) tach5 pwmout5 (tach11) tach6 pwmout6 (tach12) max31790 max31790 6-channel pwm-output fan rpm controller maxim integrated
12 figure 3. 11 fans, 11 tach monitors,1 pwm figure 4. 10 fans, 10 tach monitors, 2 pwms tach1 pwmout1 tach2 pwmout2 (tach8) tach3 pwmout3 (tach9) tach4 pwmout4 (tach10) tach5 pwmout5 (tach11) tach6 pwmout6 (tach12) max31790 tach1 pwmout1 tach2 pwmout2 (tach8) tach3 pwmout3 (tach9) tach4 pwmout4 tach5 pwmout5 (tach11) tach6 pwmout6 (tach12) max31790 max31790 6-channel pwm-output fan rpm controller maxim integrated
13 fan failure when enabled, the device monitors the tach inputs to determine when a fan has failed. for fans with tachom - eter outputs, failure is detected in various ways depend - ing on the fan control mode. in every case, from one to six consecutive fault detections (selected by the fan fault queue bits) are required to decide that the fan has failed. when the selected number of fault detections has occurred, the fan_fail output asserts (if fault detection is not masked for the fan). pwm mode failure detection in pwm mode, the tach target count register holds the upper limit for tachometer count values. a potential fault condition is identified when the tach count exceeds the value written to the tach target count register. if the fan fault queue bit value is 1 and the following tachom - eter count (1 second later) also exceeds the limit value, the fan is considered to have failed. a higher fan fault queue bit value requires a larger number of consecutive values in excess of the limit value. when a pwm output is used as a tach input, the pwm-mode failure criteria apply. in pwm mode, fan-failure detection is masked when the target duty cycle is set to zero. figure 5. 9 fans, 9 tach monitors, 3 pwms figure 6. 8 fans, 8 tach monitors, 4 pwms tach1 pwmout1 tach2 pwmout2 (tach8) tach3 pwmout3 tach4 pwmout4 tach5 pwmout5 (tach11) tach6 pwmout6 max31790 tach1 pwmout1 tach2 pwmout2 (tach8) tach3 pwmout3 tach4 pwmout4 (tach10) tach5 pwmout5 tach6 pwmout6 (tach12) max31790 max31790 6-channel pwm-output fan rpm controller maxim integrated
14 rpm mode failure detection in rpm mode, a potential fault condition is identified when any of the following three conditions occur: 1) the tach count exceeds the associated value stored in the tach target count register while the pwm duty cycle is 100%, 2) the tach count exceeds two times the tach target count register value while the duty cycle is less than 100%, or 3) the tach count reaches its maximum value of 7ffh. if the fan fault queue bit value is 1 and the tach count value also exceeds the limit value, the fan is considered to have failed. a higher fan fault queue value requires a larger number of consecutive values in excess of the limit value. in rpm mode, fan- failure detection is masked when the tach target count register is set to full scale. locked rotor mode failure detection some fans have a locked rotor output that produces a logic-level output to indicate that the fan has stopped spin - ning. locked rotor signals can be monitored by setting the tach /locked rotor bit in the associated fan configuration register. the polarity of the locked rotor signal can be adjusted in this same register. a fan fault is detected when a locked rotor signal has been present for 1 second. failure indication fan failure is indicated in the fan fault register and also with the open-drain fan_fail output after the number of consecutive faults selected by the fan fault queue bits have occurred. the fan_fail output can be masked using the mask bits in the fan fault mask register. when a fan has failed, pwm to the affected fan can continue as though the fan is still operational, or the duty cycle can be automatically set to 0 or 100% as deter - mined by the failed fan options bits. see the register descriptions section for full details. the failed condition can be cancelled by writing pwm target duty cycle or tach target count to the fans control registers. the new value can be the same as the value already in the register. after writing to the register, the fan-failure detection process begins again. if the fan is still in a failed state, fan failure again is detected. slave address byte and address pins the slave address byte consists of a 7-bit slave address plus an r/ w bit ( figure 7 ). the devices slave address is determined by the state of the add0 and add1 address pins during a start condition of an i 2 c transaction. the add0 and add1 pins can be connected to gnd, v cc , sda, or scl. these pins allow up to 16 max31790s to reside on the same i 2 c bus. see table 1 for a complete list of all 16 possibilities and the corresponding add0 and add1 pin connections. for example, the devices slave address byte is 40h when add0 and add1 pins are grounded during a start condition. i 2 c communication is described in detail in the i 2 c serial interface description section. note: if the state of the add0 and add1 pins is changing during normal operation, the slave address of the device dynamically changes to reflect the pins states at every start condition. the add0 and add1 pins cannot change during an i 2 c transaction. table 1. slave address table figure 7. max31790 slave address byte example add1 connection add0 connection slave address byte (hex) gnd gnd 40 gnd scl 42 gnd sda 44 gnd v cc 46 scl gnd 48 scl scl 4a scl sda 4c scl v cc 4e sda gnd 50 sda scl 52 sda sda 54 sda v cc 56 v cc gnd 58 v cc scl 5a v cc sda 5c v cc v cc 5e 01 0 0r /w 0 0 0 msb lsb slave address* see table 1 *the slave address is determined by address pins add0 and add1. read/write bit max31790 6-channel pwm-output fan rpm controller maxim integrated
15 memory description the devices control registers are organized in rows of 8 bytes. the i 2 c master can read or write individual bytes, or can read or write multiple bytes. when writing consecutive bytes, all writes are to the same row. when the final byte in the row is reached, the next byte written is the rows first byte. for example, a write that starts with 02h (fan 1 configuration) can write to 02h, 03h, 04h, 05h, 06h, and 07h. if writes continue, the next byte written is 00h, and so on. consecutive reads are not subject to the single-row limitation. a read can start at any address and can continue through ffh. if reads continue past ffh, they wrap around to 00h. user bytes are general-purpose r/w bytes. x denotes the input state at por. register map r/w register por state function d7 d6 d5 d4 d3 d2 d1 d0 r/w 00h 0010 0xx0b global configuration run /standby 0 = run 1 = standby reset: 0 = normal 1 = reset bus timeout 0 = enabled reserved osc: 0 = internal oscillator 1 = external crystal i 2 c watchdog: 00b = disabled 01b = 5s 10b = 10s 11b = 30s i 2 c watchdog status 1 = watchdog fault detected r/w 01h freq_start pwm frequency pwm4-pwm6 frequency: 0000b = 25hz 0001b = 30hz 0010b = 35hz 0011b = 100hz 0100b = 125hz 0101b = 149.7hz 0110b = 1.25khz 0111b = 1.47khz 1000b = 3.57khz 1001b = 5khz 1010b = 12.5khz 1011b = 25khz pwm1-pwm3 frequency: 0000b = 25hz 0001b = 30hz 0010b = 35hz 0011b = 100hz 0100b = 125hz 0101b = 149.7hz 0110b = 1.25khz 0111b = 1.47khz 1000b = 3.57khz 1001b = 5khz 1010b = 12.5khz 1011b = 25khz r/w 02h 0xx0 0000b fan 1 configuration mode: 0 = pwm 1 = rpm spin-up 00b = no spin-up 01b = 2 tach counts or 0.5s 10b = 2 tach counts or 1s 11b = 2 tach counts or 2s control /monitor 0 = control 1 = monitor only tach input enable 1 = enabled tach / locked rotor 0 = tach 1 = locked rotor locked rotor polarity 0 = low 1 = high pwm /tach 0 = pwm 1 = tach r/w 03h 0xx0 0000b fan 2 configuration same as fan 1 configuration r/w 04h 0xx0 0000b fan 3 configuration same as fan 1 configuration max31790 6-channel pwm-output fan rpm controller maxim integrated
16 register map (continued) r/w register por state function d7 d6 d5 d4 d3 d2 d1 d0 r/w 05h 0xx0 0000b fan 4 configuration same as fan 1 configuration r/w 06h 0xx0 0000b fan 5 configuration same as fan 1 configuration r/w 07h 0xx0 0000b fan 6 configuration same as fan 1 configuration r/w 08h 0100 1100b fan 1 dynamics speed range (tach periods counted) 000b = 1 001b = 2 010b = 4 (default) 011b = 8 100b = 16 101b = 32 110b = 32 111b = 32 pwm rate-of-change: 000b = 0ms per lsb (pwm) 000b = 0.9765ms per lsb (rpm) 001b = 1.953125ms per lsb 010b = 3.90625ms per lsb 011b = 7.8125ms per lsb (default) 100b = 15.625ms per lsb 101b = 31.25ms per lsb 110b = 62.5ms per lsb 111b = 125ms per lsb asymmetric rate of change 1 = enabled reserved r/w 09h 0100 1100b fan 2 dynamics same as fan 1 dynamics r/w 0ah 0100 1100b fan 3 dynamics same as fan 1 dynamics r/w 0bh 0100 1100b fan 4 dynamics same as fan 1 dynamics r/w 0ch 0100 1100b fan 5 dynamics same as fan 1 dynamics r/w 0dh 0100 1100b fan 6 dynamics same as fan 1 dynamics r/w 0eh 0000 0000b user byte r/w 0fh 0000 0000b user byte r/w 10h 0000 0000b fan fault status 2 reserved reserved fan 12 fault 1 = fault fan 11 fault 1 = fault fan 10 fault 1 = fault fan 9 fault 1 = fault fan 8 fault 1 = fault fan 7 fault 1 = fault r/w 11h 0000 0000b fan fault status 1 reserved reserved fan 6 fault 1 = fault fan 5 fault 1 = fault fan 4 fault 1 = fault fan 3 fault 1 = fault fan 2 fault 1 = fault fan 1 fault 1 = fault r/w 12h 0011 1111b fan fault mask 2 reserved reserved fan 12 mask 1 = masked fan 11 mask 1 = masked fan 10 mask 1 = masked fan 9 mask 1 = masked fan 8 mask 1 = masked fan 7 mask 1 = masked r/w 13h 0011 1111b fan fault mask 1 reserved reserved fan 6 mask 1 = masked fan 5 mask 1 = masked fan 4 mask 1 = masked fan 3 mask 1 = masked fan 2 mask 1 = masked fan 1 mask 1 = masked max31790 6-channel pwm-output fan rpm controller maxim integrated
17 register map (continued) r/w register por state function d7 d6 d5 d4 d3 d2 d1 d0 r/w 14h 0100 0101b failed fan options/ sequential start sequential start delay 000b = 0s 001b = 250ms 010b = 500ms 011b = 1s 100b = 2s 101b, 110b, 111b = 4s reserved failed fan options 00b = duty cycle = 0% on fail 01b = continue pwm or rpm mode operation on fail. 10b = duty cycle = 100% on fail 11b = all fans to 100% on any unmasked fan failure. fan faut queue 00b = 1 fault 01b = 2 faults 10b = 4 faults 11b = 6 faults r/w 15h 0000 0000b user byte r/w 16h 0000 0000b user byte r/w 17h 0000 0000b user byte r 18h 1111 1111b tach 1 count msb 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 r 19h 1110 0000b tach 1 count lsb 2 2 2 1 2 0 0 0 0 0 0 r 1ah 1111 1111b tach 2 count msb same as tach 1 count r 1bh 1110 0000b tach 2 count lsb r 1ch 1111 1111b tach 3 count msb same as tach 1 count r 1dh 1110 0000b tach 3 count lsb r 1eh 1111 1111b tach 4 count msb same as tach 1 count r 1fh 1110 0000b tach 4 count lsb r 20h 1111 1111b tach 5 count msb same as tach 1 count r 21h 1110 0000b tach 5 count lsb r 22h 1111 1111b tach 6 count msb same as tach 1 count r 23h 1110 0000b tach 6 count lsb r 24h 1111 1111b tach 7 count msb same as tach 1 count r 25h 1110 0000b tach 7 count lsb max31790 6-channel pwm-output fan rpm controller maxim integrated
18 register map (continued) r/w register por state function d7 d6 d5 d4 d3 d2 d1 d0 r 26h 1111 1111b tach 8 count msb same as tach 1 count r 27h 1110 0000b tach 8 count lsb r 28h 1111 1111b tach 9 count msb same as tach 1 count r 29h 1110 0000b tach 9 count lsb r 2ah 1111 1111b tach 10 count msb same as tach 1 count r 2bh 1110 0000b tach 10 count lsb r 2ch 1111 1111b tach 11 count msb same as tach 1 count r 2dh 1110 0000b tach 11 count lsb r 2eh 1111 1111b tach 12 count msb same as tach 1 count r 2fh 1110 0000b tach 12 count lsb r 30h 0000 0000b pwmout 1 duty cycle msb 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 r 31h 0000 0000b pwmout 1 duty cycle lsb 2 0 0 0 0 0 0 0 0 r 32h 0000 0000b pwmout 2 duty cycle msb same as pwmout 1 duty cycle r 33h 0000 0000b pwmout 2 duty cycle lsb r 34h 0000 0000b pwmout 3 duty cycle msb same as pwmout 1 duty cycle r 35h 0000 0000b pwmout 3 duty cycle lsb max31790 6-channel pwm-output fan rpm controller maxim integrated
19 register map (continued) r/w register por state function d7 d6 d5 d4 d3 d2 d1 d0 r 36h 0000 0000b pwmout 4 duty cycle msb same as pwmout 1 duty cycle r 37h 0000 0000b pwmout 4 duty cycle lsb r 38h 0000 0000b pwmout 5 duty cycle msb same as pwmout 1 duty cycle r 39h 0000 0000b pwmout 5 duty cycle lsb r 3ah 0000 0000b pwmout 6 duty cycle msb same as pwmout 1 duty cycle r 3bh 0000 0000b pwmout 6 duty cycle lsb r 3ch 0000 0000b reserved 0 0 0 0 0 0 0 0 r 3dh 0000 0000b reserved 0 0 0 0 0 0 0 0 r 3eh 0000 0000b reserved 0 0 0 0 0 0 0 0 r 3fh 0000 0000b reserved 0 0 0 0 0 0 0 0 r/w 40h pwm_start pwmout1 target duty cycle msb 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 r/w 41h pwm_start pwmout1 target duty cycle lsb 2 0 reserved reserved reserved reserved reserved reserved reserved r/w 42h pwm_start pwmout2 target duty cycle msb same as pwmout 1 target duty cycle r/w 43h pwm_start pwmout2 target duty cycle lsb r/w 44h pwm_start pwmout3 target duty cycle msb same as pwmout 1 target duty cycle r/w 45h pwm_start pwmout3 target duty cycle lsb max31790 6-channel pwm-output fan rpm controller maxim integrated
20 register map (continued) r/w register por state function d7 d6 d5 d4 d3 d2 d1 d0 r/w 46h pwm_start pwmout4 target duty cycle msb same as pwmout 1 target duty cycle r/w 47h pwm_start pwmout4 target duty cycle lsb r/w 48h pwm_start pwmout5 target duty cycle msb same as pwmout 1 target duty cycle r/w 49h pwm_start pwmout5 target duty cycle lsb r/w 4ah pwm_start pwmout6 target duty cycle msb same as pwmout 1 target duty cycle r/w 4bh pwm_start pwmout6 target duty cycle lsb r/w 4ch 0000 0000b user byte r/w 4dh 0000 0000b user byte r/w 4eh 0000 0000b user byte r/w 4fh 0000 0000b user byte r/w 50h 0011 1100b tach 1 target count msb 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 r/w 51h 0000 0000b tach 1 target count lsb 2 2 2 1 2 0 reserved reserved reserved reserved reserved r/w 52h 0011 1100b tach 2 target count msb same as tach 1 target count r/w 53h 0000 0000b tach 2 target count lsb r/w 54h 0011 1100b tach 3 target count msb same as tach 1 target count r/w 55h 0000 0000b tach 3 target count lsb max31790 6-channel pwm-output fan rpm controller maxim integrated
21 register map (continued) x = input state at por. r/w register por state function d7 d6 d5 d4 d3 d2 d1 d0 r/w 56h 0011 1100b tach 4 target count msb same as tach 1 target count r/w 57h 0000 0000b tach 4 target count lsb r/w 58h 0011 1100b tach 5 target count msb same as tach 1 target count r/w 59h 0000 0000b tach 5 target count lsb r/w 5ah 0011 1100b tach 6 target count msb same as tach 1 target count r/w 5bh 0000 0000b tach 6 target count lsb r/w 5ch 0000 0000b user byte r/w 5dh 0000 0000b user byte r/w 5eh 0000 0000b user byte r/w 5fh 0000 0000b user byte r/w 60h 0000 0000b window 1 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 r/w 61h 0000 0000b window 2 same as window 1 r/w 62h 0000 0000b window 3 same as window 1 r/w 63h 0000 0000b window 4 same as window 1 r/w 64h 0000 0000b window 5 same as window 1 r/w 65h 0000 0000b window 6 same as window 1 r/w 66h 0000 0000b user byte r/w 67h 0000 0000b user byte max31790 6-channel pwm-output fan rpm controller maxim integrated
22 register descriptions x = input state at por. global configuration register (00h) power-on value 0010 0xx0b read access all write access all memory type volatile 00h run / standby reset bus timeout reserved osc i 2 c watchdog i 2 c watchdog status bit 7 bit 0 bit 7 run /standby: places the device in standby mode. 0 = run 1 = standby entering standby mode sets all pwm duty cycles to 0 and stops fan failure detection. however, driving the full_speed input low forces all enabled pwmout outputs high (100% duty cycle) regardless of the state of the run bit. bit 6 reset: 0 = normal operation 1 = reset all registers to por value this bit automatically resets itself and always returns a 0 when read. bit 5 bus timeout : i 2 c bus timeout. 0 = enabled 1 = disabled the i 2 c interface resets if sda is low for more than 35ms. bit 4 reserved bit 3 oscillator selection: 0 = internal oscillator (default at power-on) 1 = external 32.768khz crystal selects on-chip oscillator or external 32.768khz crystal/ceramic resonator for tach count and source for clkout pin. use crystal or ceramic resonator if higher accuracy is required. when switching from the internal oscillator to an external crystal, the device operates from the internal oscillator until the crystal oscillator has started up. if the crystal is damaged or the oscillator fails to start, the device continues to operate from the internal oscillator. max31790 6-channel pwm-output fan rpm controller maxim integrated
23 bits 2:1 i 2 c watchdog: when active, the watchdog monitors sda and scl for valid i 2 c transactions. if there are no valid transactions between the master and the device within the watchdog period, all fan pwm outputs go to 100%. if the watchdog times out and valid i 2 c transactions begin to occur again, operation resumes with the previous pwm value. the master can then program the pwm outputs, target tach counts, or other functions in the normal manner. when the watchdog function is active, ensure that the master communicates to the device periodically, for example, reading a status register. the por state is set by the state of the wd_start pin at power-up. bits 2:1 i 2 c watchdog period (s) por condition 00b inactive (no watchdog) wd_start = gnd 01b 5 10b 10 11b 30 wd_start = v cc bit 0 i 2 c watchdog status: 0 = i 2 c transactions occurred within watchdog period 1 = time between i 2 c transaction exceeds watchdog period clear this bit by writing a 0 to it. max31790 6-channel pwm-output fan rpm controller maxim integrated
24 pwm frequency register (01h) power-on value xxxx xxxxb read access all write access all memory type volatile 01h pwm4-pwm6 frequency pwm1-pwm3 frequency bit 7 bit 0 bits 7:4 pwm4-pwm6 frequency: these bits select the pwm out frequency for pwmout4, pwmout5, and pwmout6 according to the following: bits 7:4 pwm ouput frequency por condition 0000b 25hz 0001b 30hz freq_start = gnd 0010b 35hz 0011b 100hz 0100b 125hz 0101b 149.7hz 0110b 1.25khz 0111b 1.47khz freq_start = unconnected 1000b 3.57khz 1001b 5khz 1010b 12.5khz 1011b 25khz freq_start = v cc the por state is set by the state of the freq_start pin at power-up as shown. bits 3:0 pwm1-pwm3 frequency: these bits select the pwm out frequency for pwmout1, pwmout2, and pwmout3 according to the following: bits 7:4 pwm ouput frequency por condition 0000b 25hz 0001b 30hz freq_start = gnd 0010b 35hz 0011b 100hz 0100b 125hz 0101b 149.7hz 0110b 1.25khz 0111b 1.47khz freq_start = unconnected 1000b 3.57khz 1001b 5khz 1010b 12.5khz 1011b 25khz freq_start = v cc the por state is set by the state of the freq_start pin at power-up as shown. max31790 6-channel pwm-output fan rpm controller maxim integrated
25 fan 1 configuration register (02h) fan 2 configuration register (03h) fan 3 configuration register (04h) fan 4 configuration register (05h) fan 5 configuration register (06h) fan 6 configuration register (07h) power-on value 0xx0 0000b read access all write access all memory type volatile 02h, 03h, 04h, 05h, 06h, 07h mode spin-up control / monitor tach input enable tach / locked rotor locked rotor polarity pwm / tach bit 7 bit 0 bit 7 mode: rpm/pwm mode select. 0 = pwm mode. pwm duty cycle is set by the value in the associated pwmout target duty cycle register. 1 = rpm mode. the pwm duty cycle is adjusted to produce the tach count value in the associated tach target count register. when changing from pwm to rpm mode, if the current rpm value is different from the value selected in the tach target count register, the pwm duty cycle starts from the current value and increment/decrements toward the desired value at the selected duty cycle rate-of-change. bits 6:5 spin-up: when spin-up is selected and the fan is started with a target pwm duty cycle less than 100%, the device produces 100% duty cycle until two tachometer pulses have been detected. a maximum spin-up time is also selectable to ensure that the spin-up time is not excessive. after two tachometer pulses have been detected, or the spin-up has timed out, the duty cycle goes to the value in the pwmout target duty cycle register. the por state is set by the state of the spin_start pin at power-up. bits 6:5 spin-up behavior por condition 00b no spin-up spin_start = gnd 01b spin-up until two tachometer pulses or 0.5s (max) spin_start = unconnected 10b spin-up until two tachometer pulses or 1s (max) spin_start = v cc 11b spin-up until two tachometer pulses or 2s (max) bit 4 control /monitor: 0 = control fan speed. 1 = monitor only. associated duty cycle = 0% regardless of other settings; monitor associated tach or locked rotor if enabled by bit 3. max31790 6-channel pwm-output fan rpm controller maxim integrated
26 bit 3 tach input enable: enables associated tach input function and fan fault detection (automatically enabled in rpm mode). 0 = disabled. when disabled and tach input is not used, bits 1 and 2 are ignored. 1 = enabled bit 2 tach /locked rotor: selects tach input function as tach count or locked rotor. in locked rotor mode, assertion of the associated tach input indicates that the fan has stopped. 0 = tach count 1 = locked rotor bit 1 locked rotor polarity: 0 = low locked rotor. associated tach input low in locked rotor mode indicates fan is stopped. 1 = high locked rotor. associated tach input high in locked rotor mode indicates fan is stopped. bit 0 pwm /tach: when set to 0, the associated pwmout produces a pwm waveform for control of fan speed. when set to 1, pwmout becomes a tach input whose channel number is equal to the number of the pwmout channel plus six. max31790 6-channel pwm-output fan rpm controller maxim integrated
27 fan 1 dynamics register (08h) fan 2 dynamics register (09h) fan 3 dynamics register (0ah) fan 4 dynamics register (0bh) fan 5 dynamics register (0ch) fan 6 dynamics register (0dh) power-on value 0100 1100b read access all write access all memory type volatile 08h, 09h, 0ah, 0bh, 0ch, 0dh speed range pwm rate-of-change asymmetric rate of change reserved bit 7 bit 0 bits 7:5 speed range: the device determines fan speed by counting the number of internal 8192hz (f tosc /4) clock cycles (using an 11-bit counter) during one or more fan tachometer periods. three bits set the nominal rpm range for the fan, as shown in the table below. for example, a setting of 010b causes the device to count the number of 8192hz (f tosc /4) clock cycles that occur during four complete tachometer periods. if the fan has a nominal speed of 2000 rpm and two tachometer pulses per revolution, one tachometer period is nominally 15ms, and four tachometer periods are 60ms. with an 8192hz (f tosc /4) clock, the tach count is therefore equal to 491. with a fan speed of 1/3 the nominal value, the count is 1474. if the fans nominal speed is 1000 rpm, the full-speed tach count is 983. at 1/3 the nominal speed, there are 2948 clock cycles in four tachometer periods. this is greater than the maximum 11-bit count of 2047, so four tachometer periods is too many for this fan; a setting of 001 (two clock cycles) is recommended instead. the table below shows the full-speed tachometer counts for several combinations of nominal fan speeds and bits 7:5 settings. the shaded combinations provide the best results. nonshaded combinations should generally be avoided. when setting bits 7:5, the goal is to obtain the highest tachometer count without exceeding the maximum count of 2047 when the fan is at the minimum speed of interest. for example, if the minimum speed of interest is 1/3 of full speed, the maximum tachometer count is three times the value shown in the table. bits 7:5 number of tach periods counted rpm 500 1000 2000 4000 8000 16000 000b 1 491 (60ms) 245 (30ms) 122 (15ms) 61 (7.5ms) 30 (3.75ms) 15 (1.875ms) 001b 2 983 (120ms) 491 (60ms) 245 (30ms) 122 (15ms) 61 (7.5ms) 30 (3.75ms) 010b (default) 4 1966 (240ms) 983 (120ms) 491 (60ms) 245 (30ms) 122 (15ms) 61 (7.5ms) 011b 8 2047 (480ms) 1966 (240ms) 983 (120ms) 491 (60ms) 245 (30ms) 122 (15ms) 100b 16 2047 (960ms) 2047 (480ms) 1966 (240ms) 983 (120ms) 491 (60ms) 245 (30ms) 101b, 110b, 111b 32 2047 (1920ms) 2047 (960ms) 2047 (480ms) 1966 (240ms) 983 (120ms) 491 (60ms) max31790 6-channel pwm-output fan rpm controller maxim integrated
28 bits 4:2 pwm rate-of-change: pwm duty cycle rate of change. the pwm duty cycle at the associated pwmout outputs varies from 0 to full scale in 512 increments. the rate-of-change bits determine the time interval between duty cycle output increments/decrements. regardless of the settings, there are a few cases for which the rate- of-change is always 0: in rpm mode, when a tach target count of 2047 (7ffh) is selected, the duty cycle immediately goes to 0%. a full-scale target count is assumed to mean that the intent is to shut down the fan, and going directly to 0% avoids the possibility of loss of control-loop feedback at high tach counts. if a slow-speed decrease toward 0% is desired, select a tach target count at the slowest practical value for the fan. once that count has been reached, selecting a count of 2047 (7ff) then takes the drive immediately to 0%. in pwm mode, when a target duty cycle of 0% is selected, the duty cycle goes to 0%. again, it is assumed that the intent is to shut down the fan. if a slow-speed decrease toward 0% is desired, a target duty cycle of the slowest practical value for the fan in question should be chosen. once that duty cycle has been reached, selecting a target value of 0% then takes the drive immediately to 0%. when the current duty cycle is 0% in pwm mode, selecting a new target duty cycle immediately takes the duty cycle to that value. the fan spins up first if spin-up is enabled. when the current duty cycle is 0% in rpm mode, selecting a new tach target count that is less than 2047 (7ffh) immediately takes the duty cycle to the value in the pwmout target duty cycle register. from this value, the duty cycle increments as needed to achieve the desired tach target count. the fan spins up first if spin-up is enabled. bits 4:2 time between duty cycle increments (ms) rpm time from 33% to 100% (s) pwm rpm pwm rpm 000b 0 0.9765 0 0.33 001b 1.953125 0.67 010b 3.90625 1.34 011b (default) 7.8125 2.7 100b 15.625 5.3 101b 31.25 10.7 110b 62.5 21.4 111b 125 42.8 bit 1 asymmetric rate of change: 0 = same rate of change whether duty cycle is increasing or decreasing. 1 = rate of change when duty cycle is decreasing is half the rate when increasing. bit 0 reserved max31790 6-channel pwm-output fan rpm controller maxim integrated
29 user byte register (0ehC0fh) user byte register (15hC17h) user byte register (4chC4fh) user byte register (5chC5fh) user byte register (66hC67h) fan fault status 2 register (10h) power-on value 0000 0000b read access all write access all memory type volatile 0eh, 0fh, 15h, 16h, 17h, 4ch, 4dh, 4eh, 4fh, 5ch, 5dh, 5eh, 5fh, 66h, 67h bit 7 bit 0 general-purpose volatile bits. these bits have no affect on the device operation. power-on value 0000 0000b read access all write access all memory type volatile 10h reserved reserved fan 12 fault fan 11 fault fan 10 fault fan 9 fault fan 8 fault fan 7 fault bit 7 bit 0 bits 7:6 reserved bits 5:0 fan [12:7] fault: this register applies only to pwmouts that are being used as tach inputs. the associated fan experienced faults as defined in the fan failure section. when a fan fault is detected, the associated fault bit is set to 1. the fault bits latch until they are cleared by writing a pwm target duty cycle or tach target count to the associate fans control register, thus allowing short-term faults to be identified. max31790 6-channel pwm-output fan rpm controller maxim integrated
30 fan fault status 1 register (11h) fan fault mask 2 register (12h) power-on value 0000 0000b read access all write access all memory type volatile 11h reserved reserved fan 6 fault fan 5 fault fan 4 fault fan 3 fault fan 2 fault fan 1 fault bit 7 bit 0 bits 7:6 reserved bits 5:0 fan [6:1] fault: the associated fan experienced faults as defined in the fan failure section. when a fan fault is detected, the associated fault bit is set to 1. the fault bits latch until they are cleared by writing a pwm target duty cycle or tach target count to the fans control register, thus allowing short-term faults to be identified. power-on value 0011 1111 b read access all write access all memory type volatile 12h reserved reserved fan 12 mask fan 11 mask fan 10 mask fan 9 mask fan 8 mask fan 7 mask bit 7 bit0 bits 7:6 reserved bits 5:0 fan [12:7] mask: this register applies only to pwmouts that are being used as tach inputs. these bits mask faults on selected fans from asserting the fan_fail output. faults are still indicated by the fault status bits: 0 = not masked 1 = masked when a fan fails, the pwm behavior is controlled by the failed fan options register. max31790 6-channel pwm-output fan rpm controller maxim integrated
31 fan fault mask 1 register (13h) power-on value 0011 1111b read access all write access all memory type volatile 13h reserved reserved fan 6 mask fan 5 mask fan 4 mask fan 3 mask fan 2 mask fan 1 mask bit 7 bit0 bits 7:6 reserved bits 5:0 fan [6:1] mask: these bits mask faults on selected fans from asserting the fan_fail output. faults are still indicated by the fault status bits: 0 = not masked 1 = masked when a fan fails, the pwm behavior is controlled by the failed fan options register. max31790 6-channel pwm-output fan rpm controller maxim integrated
32 failed fan options/sequential start register (14h) power-on value 0100 0101b read access all write access all memory type volatile 14h sequential start delay reserved failed fan options fan fault queue bit 7 bit 0 bits 7:5 sequential start delay: note that faults are not monitored until the channel is activated after its associated start delay. these bits select the time delay between fan activations according to the following: bits 7:5 time between sequential fan startup 000b 0s 001b 250ms 010b (default) 500ms 011b 1s 100b 2s 101b 110b 111b 4s bit 4 reserved bits 3:2 failed fan options: these bits select the behavior following a fan failure according to the following: bits 3:2 set duty cycle on failure 00b 0% 01b continue current pwm or rpm mode operation 10b 100% on failed fan 11b all fans to 100% on any unmasked fan failure bits 1:0 fan fault queue: these bits select the number of consecutive fault detections that are required to decide that the fan has failed according to the following: bits 1:0 number of qualified faults 00b 1 01b 2 10b 4 11b 6 when the selected number of fault detections has occurred, the fan_fail output asserts (if fault detection is not masked for the fan). note: fan fault queue has no effect on the locked rotor fan- failure detection. max31790 6-channel pwm-output fan rpm controller maxim integrated
33 tach 1 count registers (18hC19h) tach 2 count registers (1ahC1bh) tach 3 count registers (1chC1dh) tach 4 count registers (1ehC1fh) tach 5 count registers (20hC21h) tach 6 count registers (22hC23h) tach 7 count registers (24hC25h) tach 8 count registers (26hC27h) tach 9 count registers (28hC29h) tach 10 count registers (2ahC2bh) tach 11 count registers (2chC2dh) tach 12 count registers (2ehC2fh) power-on value 1111 1111b (msb) 1110 0000b (lsb) read access all write access n/a memory type volatile 18h, 1ah, 1ch, 1eh, 20h, 22h, 24h, 26h, 28h, 2ah, 2ch, 2eh 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 19h, 1bh, 1dh, 1fh, 21h, 23h, 25h, 27h, 29h, 2bh, 2dh, 2fh 2 2 2 1 2 0 0 0 0 0 0 bit 7 bit 0 indicates the associated number of 8192hz (f tosc /4) clock pulses counted during the counting period. the tach count register consists of 11 bits, left-justified, contained in 2 bytes. the lower 5 bits always return zeros. to minimize noise from spurious tachometer transitions, pulses less that t tachmin are ignored. the tach 7 count to tach 12 count registers apply only to pwmouts that are being used as tach inputs. max31790 6-channel pwm-output fan rpm controller maxim integrated
34 pwmout 1 duty cycle (30hC31h) pwmout 2 duty cycle (32hC33h) pwmout 3 duty cycle (34hC35h) pwmout 4 duty cycle (36hC37h) pwmout 5 duty cycle (38hC39h) pwmout 6 duty cycle (3ahC3bh) power-on value 0000 0000b (msb) 0000 0000b (lsb) read access all write access n/a memory type volatile 30h, 32h, 34h, 36h, 38h, 3ah 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 31h, 33h, 35h, 37h, 39h, 3bh 2 0 0 0 0 0 0 0 fs bit 7 bit 0 this is a 9-bit left-justified value that ranges from 0 to 511 and is contained in 2 bytes. this register shows the actual pwm duty cycle for the associate pwm output. when the value is 511 (decimal), the duty cycle is 100%. the 6:1 bits always return zeros. register does not apply when associated pwmouts are being used as tach inputs. the register value is converted to the duty cycle at the fan as follows: bits 15:7 pwm duty cycle (%) decimal hex 0 000h 0 200 0c8h 39 300 12ch 59 400 190h 78 480 1e0h 94 511 1ffh 100 when duty cycle reaches 100%, bit 0 is set to a 1. max31790 6-channel pwm-output fan rpm controller maxim integrated
35 pwmout 1 target duty cycle (40hC41h) pwmout 2 target duty cycle (42hC43h) pwmout 3 target duty cycle (44hC45h) pwmout 4 target duty cycle (46hC47h) pwmout 5 target duty cycle (48hC49h) pwmout 6 target duty cycle (4ahC4bh) power-on value xxxx xxxxb (msb) x000 0000b (lsb) read access all write access all memory type volatile 40h, 42h, 44h, 46h, 48h, 4ah 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 41h, 43h, 45h, 47h, 49h, 4bh 2 0 reserved reserved reserved reserved reserved reserved reserved bit 7 bit 0 this is a 9-bit left-justified value that ranges from 0 to 511 and is contained in 2 bytes. in pwm mode, write the desired pwm duty cycle to these two registers. the device then increments the duty cycle to this value at a rate determined by the pwm duty cycle rate-of-change bits. in rpm mode, the value contained in this register is the duty cycle at pwmout immediately after spin-up or after changing the tach target count from 2047 (7ff) to any value lower than 2047 (7ff). for example, if the fan is currently stopped with spin-up disabled, and a new tach target count corresponding to 60% of the full-scale fan speed is to be selected, the duty cycle can be programmed to immediately go to 60% when the new tach target count is selected, and then close the rpm control loop starting from that duty cycle. the register value is converted to the duty cycle at the fan as follows: bits 15:7 pwm duty cycle (%) decimal hex 0 000h 0 200 0c8h 39 300 12ch 59 400 190h 78 480 1e0h 94 511 1ffh 100 the value of the pwmout target duty cycle at por depends on the state of the pwm_start0 and pwm_ start1 inputs as follows: por condition pwm_start0 pwm_start1 pwm duty cycle (%) gnd gnd 0 gnd unconnected 30 gnd v cc 40 unconnected gnd 50 unconnected v cc 60 v cc gnd 75 v cc v cc 100 max31790 6-channel pwm-output fan rpm controller maxim integrated
36 tach 1 target count (50hC51h) tach 2 target count (52hC53h) tach 3 target count (54hC55h) tach 4 target count (56hC57h) tach 5 target count (58hC59h) tach 6 target count (5ahC5bh) power-on value 0011 1100b (msb) 0000 0000b (lsb) read access all write access all memory type volatile 50h, 52h, 54h, 56h, 58h, 5ah 2 10 2 9 2 8 2 7 2 6 2 5 2 4 2 3 51h, 53h, 55h, 57h, 59h, 5bh 2 2 2 1 2 0 reserved reserved reserved reserved reserved bit 7 bit 0 this is an 11-bit left-justified value that is contained in 2 bytes. it indicates the desired number of 8192hz (f tosc /4) clock pulses counted during the counting period. in rpm mode, write the desired tachometer count to this register. the device then adjusts the associated pwm duty cycle to achieve this tachometer count. in pwm mode, this register is not used as part of the fan control algorithm. in both pwm and rpm modes, this register is used to determine fan faults. see the fan faults register description for details. when changing from pwm mode to rpm mode, best results are obtained by loading this register with the current tach count before changing to rpm mode. the tach target count for a given rpm is obtained by the following equation: 60 tach count sr 8192 np rpm = where: np = number of tach pulse per revolution sr = 1, 2, 4, 8, 16, 32 (see the speed range bit information in the associated fan dynamics register) max31790 6-channel pwm-output fan rpm controller maxim integrated
37 window 1 register (60h) window 2 register (61h) window 3 register (62h) window 4 register (63h) window 5 register (64h) window 6 register (65h) power-on value 0000 0000b read access all write access all memory type volatile 60h, 61h, 62h, 63h, 64h, 65h 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 bit 7 bit 0 when the fans speed is near the target speed in rpm modethat is, when the tach count is near the corresponding tach target countthe control loop dynamics can often be improved by slowing the rate of change of the pwm duty cycle. this operates as follows: first, set a value for the count window and store it in the appropriate window register. in rpm mode, calculate the difference between the current tach count and the target tach count. if the absolute value of this difference is less than the value in the window register, then the update rate of the pwm duty cycle is slowed to 1 lsb per second. when the current tach count falls outside of the window, the duty cycle rate of change reverts to the selected value. note: when operating in pwm mode, the window value is typically set to 0. max31790 6-channel pwm-output fan rpm controller maxim integrated
38 i 2 c serial interface description i 2 c definitions the following terminology is commonly used to describe i 2 c data transfers. see the timing diagram ( figure 1 ) and the i 2 c ac electrical characteristics table for additional information. master device: the master device controls the slave devices on the bus. the master device generates scl clock pulses and start and stop conditions. slave devices: slave devices send and receive data at the masters request. bus idle or not busy: time between stop and start conditions when both sda and scl are inac - tive and in their logic-high states. start condition: a start condition is generated by the master to initiate a new data transfer with a slave. transitioning sda from high to low while scl remains high generates a start condition. stop condition: a stop condition is generated by the master to end a data transfer with a slave. transitioning sda from low to high while scl remains high generates a stop condition. repeated start condition: the master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. a repeated start condition is issued identi - cally to a normal start condition. bit write: transitions of sda must occur during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the setup and hold time requirements. data is shifted into the device during the rising edge of the scl. bit read: at the end of a write operation, the master must release the sda bus line for the proper amount of setup time before the next rising edge of scl dur - ing a bit read. the device shifts out each bit of data on sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the cur - rent scl pulse. remember that the master generates all scl clock pulses including when it is reading bits from the slave. acknowledgement (ack and nack): an acknowl - edgement (ack) or not-acknowledge (nack) is always the 9th bit transmitted during a byte trans - fer. the device receiving data (the master during a read or the slave during a write operation) performs an ack by transmitting a zero during the 9th bit. a device performs a nack by transmitting a one (done by releasing sda) during the 9th bit. the timing ( figure 1 ) for the ack and nack is identical to all other bit writes. an ack is the acknowledgment that the device is properly receiving data. a nack is used to terminate a read sequence or as an indication that the device is not receiving data. byte write: a byte write consists of 8 bits of informa - tion transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. the 8 bits transmitted by the master are done according to the bit write definition and the acknowledgement is read using the bit read definition. byte read: a byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ack or nack from the master to the slave. the 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition, and the master transmits an ack using the bit write definition to receive additional data bytes. the master must nack the last byte read to terminate communication so the slave returns control of sda to the master. slave address byte: each slave on the i 2 c bus responds to a slave address byte sent immediately following a start condition. the slave address byte contains the slave address in the most significant 7 bits and the r/ w bit in the least significant bit. see the slave address byte and address pins section for details on the max31790s slave address. if an incorrect (nonmatching) slave address is written, the max31790 assumes the master is communicating with another i 2 c device and ignores the communica - tion until the next start condition is sent. memory address: during an i 2 c write operation to the max31790, the master must transmit a memory address to identify the memory location where the slave is to store the data. the memory address is always the second byte transmitted during a write operation following the slave address byte. max31790 6-channel pwm-output fan rpm controller maxim integrated
39 i 2 c communication see figure 8 for i 2 c communication examples. writing a single byte to a slave: the master must generate a start condition, write the slave address byte (r/ w = 0), write the memory address, write the byte of data, and generate a stop condition. the master must read the slaves acknowledgement dur - ing all byte write operations. reading a single byte from a slave: unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. to read a single byte from the slave, the master generates a start condition, writes the slave address byte with r/ w =1, reads the data byte with a nack to indicate the end of the transfer, and generates a stop condition. however, since requir - ing the master to keep track of the memory address counter is impractical, the following method should be used to perform reads from a specified memory location. manipulating the address counter for reads: a dummy write cycle can be used to force the address counter to a particular value. to do this, the mas - ter generates a start condition, writes the slave address byte (r/ w = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (r/ w = 1), reads data with ack or nack as applicable, and generates a stop condition. recall that the master must nack the last byte to inform the slave that no additional bytes are to be read. reading multiple bytes from a slave: the read operation can be used to read multiple bytes with a single transfer. when reading bytes from the slave, the master simply acks the data byte if it desires to read another byte before terminating the transaction. after the master reads the last byte it must nack to indicate the end of the transfer and generates a stop condition. figure 8. i 2 c communication examples start start stop slave ack slave ack stop single-byte write -write 00h to register 0eh single-byte read -read register 0eh repeated start master nack 0100000 0 40h 00001110 0eh slave ack start slave ack 0100000 0 40h 0 1000001 41h 00001110 0eh slave ack slave ack stop 00000000 00h stop slave ack stop 01110101 75h start slave ack 0100000 0 40h 00001110 0eh slave ack slave ack 00000001 01h slave ack data in 0eh data repeated start master ack start slave ack 0100000 0 40h 0 1000001 41h 00001110 0eh slave ack slave ack data in 0eh data master nack data in 0fh data example i 2 c transactions with 40h as the device address (when add0 and add1 are connected to gnd) *the slave address is determined by address pins add0 and add1. typical i 2 c write transaction a) 2-byte write -write 0eh and 0fh to 01h and 75h c) b) 2-byte read -read 0eh and 0fh d) msb lsb b7 b6 b5 b4 b3 b2 b1 b0 register address msb lsb b7 b6 b5 b4 b3 b2 b1 b0 data slave ack slave ack slave address* 010 r/w msb lsb read/ write see table 1 max31790 6-channel pwm-output fan rpm controller maxim integrated
40 applications information controlling 4-wire fans (pwm mode) initial settings: ? begin with the por settings. ? write the desired number of tachometer periods to be counted in the speed range bits (7:5 of the cor - responding fan dynamics register). ? write the maximum allowable tachometer count to the corresponding tach target count register. tachometer counts greater than this value results in a fan fault detection. choose a value that is not encoun - tered during normal operation, accounting for normal fan speed tolerances. ? set the tach input enable bit in the corresponding fan configuration register to 1. note: this bit can be set after the fan has been started, if desired. if the bit is set before writing a pwmout target duty cycle, the duty cycle should be set immediately after enabling the tach input to avoid failure detection before the fan has started spinning. starting the fan: ? write the desired duty cycle value to the correspond - ing pwmout target duty cycle register. changing speeds: ? write the new desired duty-cycle value to the corre - sponding pwmout target duty cycle register. stopping the fan: ? write a duty cycle value of 0% to the pwmout target duty cycle register. ? if a gradual decrease in fan speed is desired, write the lowest duty cycle at which the fan can reliably operate. when the duty cycle reaches that value, write 0% to the pwmout target duty cycle register. controlling 4-wire fans (rpm mode) begin as in pwm mode and start the fan. changing from pwm mode to rpm mode: ? write the desired tachometer count to the corre - sponding tach target count registers. ? set bit 7 of the corresponding fan configuration reg - ister to 1. this selects rpm mode. the fan goes to the selected tach target count. changing speeds: ? write the desired tachometer count to the corre - sponding tach target count register. stopping the fan: ? set the tach target count value to full scale. the pwm duty cycle immediately goes to 0%. or: ? write the current duty cycle into the corresponding pwmout target duty cycle register. ? write a value greater than the current tachometer count into the tach target count register. ? write a 0 to bit 7 of the corresponding fan configuration register. this selects pwm mode. ? write a duty cycle value of 0% to the pwmout target duty cycle register. ? if a gradual decrease in fan speed is desired, write the lowest duty cycle at which the fan can reliably operate. when the duty cycle reaches that value, write 0 to the pwmout target duty cycle register. controlling 2-wire and 3-wire fans although the device is optimized for use with fans that have speed-control inputs (generally referred to as 4-wire fans), it can also be used with fans that have no speed- control inputs. when a fan has no speed-control input, its speed can be controlled by modulating the fans power- supply voltage. one approach is shown in figure 9 , where the pwm output of the fan is lowpass filtered and converted to a variable dc voltage that powers the fan. the highest available pwm frequency should be used. this approach works well with a wide variety of fans. because the fans supply current must pass through the mosfet, this approach is best with lower power fans that use on the order of 200ma or less supply current. for higher power fans, more efficient dc drive can be generated using a low-cost dc-dc converter. a dc-dc converter can be used to efficiently transform the devices pwmout signal into a variable power supply for the fan, as shown in figure 10 . max31790 6-channel pwm-output fan rpm controller maxim integrated
41 figure 9. high-side linear drive circuit for 2-wire or 3-wire fans figure 10. using a low-cost dc-dc converter to efficiently transform pwmout signal into variable power supply for the fan max31790 3.3v pwmout1 0.1f 2.2f 10f 3.3v v fan 3.3v tach1 tach output tach output 3.3v 4.7k 4.7k 91k 100k 2n3904 100k 33k max31790 33063a 3.3v pwmout1 0.1f tach1 3.3v 4.7k i pk v cc tc in d1 1n5819 l1 47h d gnd c e r3 0.5 r2 3.6k r1a 1.2k c4 0.1 f c2 470 f c3 47 f +20v c1 470pf max31790 6-channel pwm-output fan rpm controller maxim integrated
42 a simpler approach to driving a 2-wire or 3-wire fan, although with important limitations, is to modulate the fans power supply with the pwm signal. in this case, a low pwm frequency (typically in the 30hz range) is used to drive the gate of an n-channel mosfet, which provides the connection between the fan and the power supply ground, as shown in figure 11 . there are three important disadvantages to this approach. first, the rapid application and removal of the supply voltage when modulated at a 30hz rate causes an audible increase in fan noise. second, some fan vendors recommend against modulating the power supply with a pwm output because of reliability concerns. check with your fan ven - dor to confirm that this approach is compatible with the fan you plan to use. third, when using a 3-wire fan, the tach signal is modulated by the pwm signal, making the tach signal difficult to use for closed-loop speed control. power-supply decoupling to achieve the best results when using the max31790, decouple the power supply with a 0.01 f f or 0.1 f f capacitor. use a high-quality ceramic surface-mount capacitor if possible. surface-mount components mini - mize lead inductance, which improves performance, and ceramic capacitors tend to have adequate high fre - quency response for decoupling applications. layout considerations the crystal should be placed very close to the device to minimize excessive loading due to parasitic capaci - tances. care should also be taken to minimize loading on pins that could be left unconnected as a programming option (spin_start, pwm_start0, pwm_start1, freq_start). coupling on inputs due to clocks should be minimized. ordering information packaging information for the latest package outline information and land patterns (foot - prints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. figure 11. controlling the speed of a 2-/3-wire fan by pulse- width modulating the fans power-supply voltage + denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. * ep = exposed pad. part temp range pin-package MAX31790ATI+ -40 n c to +125 n c 28 tqfn-ep* MAX31790ATI+t -40 n c to +125 n c 28 tqfn-ep* package type package code outline no. land pattern no. 28 tqfn-ep t2844+1 21-0139 90-0035 max31790 3.3v tach1 0.1f 3.3v v fan 3.3v pwmout1 tach output 3.3v 4.7k 4.7k max31790 6-channel pwm-output fan rpm controller maxim integrated
maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 43 ? 2012 maxim integrated products, inc. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. revision history revision number revision date description pages changed 0 12/12 initial release max31790 6-channel pwm-output fan rpm controller

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